1. Field of the Invention
The present invention relates to a pseudo continuous tone process apparatus for causing a display to display continuous tones in an error diffusion manner, wherein the display displays images based on predetermined bits of image display data, and the continuous tones are displayed using a higher number of bits than the predetermined number of bits in a pseud manner. In particular, this pseudo continuous tone process apparatus utilizes finer continuous tones than the continuous tones displayable by an LCD display having a digital driver for input of a predetermined number of bits, so that the display can display images which are closer to original images.
2. Description of the Prior Art
Recently, a high precision color liquid crystal display for a multimedia use has been developed for office automation. Such color liquid crystals each include a three or four bit digital driver with respect to each of R, G, and B colors. For instance, a color liquid crystal having a three bit digital driver can display eight levels of tones for each color, i.e., 512 colors in total. Such a display is sufficiently usable when it is used simply as a monitor for office automation. However, it is insufficient for displaying motion or still images for a multimedia use, and an increase of the number of continuous tones displayable has thus been desired.
In order to solve this problem, the following methods have conventionally been employed to increase the number of continuous tones displayable in a pseudo manner: a method wherein an undisplayable component with one pixel is diffused into its surrounding adjacent pixels in the same screen frame (inner-frame error diffusion), and a method wherein such a component is diffused into identical pixels over a plurality of screen frames (inter-frame error diffusion). In this application, "error data" signifies data for the lower bit(s) of image data, the lower bit data being unable to be displayed via the digital driver of the display in use.
FIG. 1 is a block diagram showing a multi-continuous tone process circuit using inner-frame error diffusion, for one color among R, G, and B.
In this diagram, a latch circuit 1 sequentially receives eight bit original image data SD in synchronism with a dot clock DCLK and latches them. It then supplies the data SD into an adding circuit 2. The adding circuit 2 in turn adds the lower data SD and four bit error data EI to thereby make eight bit corrected image data HD. An error data hold circuit 3 receives the lower four bits of the corrected image data HD as error data EI according to a dot clock DCLK and holds them for subsequent use in inner-frame error diffusion. A circuit 3 outputs the error data EI to the adding circuit 2 when the original data SD for the next pixel is latched in latch circuit 1. The upper four bits of the corrected image data HD are held in an output latch circuit 4 as a result of inner-frame error diffusion and then outputted to a display as image display data DG. As outlined above, the adding circuit 2 and the error data hold circuit 3 together constitute an inner-frame error diffusion circuit. In this circuit, original image data SD is added to error data EI of a prior pixel by one dot in the adding circuit 2, so that the error data of the lower four bits of the previous pixel is sequentially diffused into its adjacent subsequent pixels. As the result of such sequential diffusion of errors, the fineness of continuous tones displayable is increased in a pseudo manner.
As described above, when four bit image display data DG for respective R, G, and B colors are supplied after being subjected to error diffusion processing into a liquid crystal display which incorporates a digital driver for four bit input, it is possible to display continuous 256.times.256.times.256 tones in a pseudo manner.
The above is an outline of a multi-continuous tone image process apparatus which utilizes inner-frame error diffusion. For more details, Japanese Patent Application No. Hei 4-307210 filed by the present applicant is available for reference.
In the aforementioned pseudo continuous tone process apparatus, error diffusion is made through adding processing in the horizontal direction. Thus, an image may influence the image on its right, resultantly affecting the entire image display data on the display panel. For displaying a moving image or an image expressed in varying densities, this pseudo continuous tone processing is advantageous, significantly improving the image quality. However, for displaying an image expressed in rather flat densities, such as the sky or a human face, image data for a discontinuous image will bring about an error which is made based on that image data, and this will eventually cause a visible trace in a displayed image on the right side of the discontinuous image, ruining the whole display quality.
Assume a case where a mouse cursor is moved on a computer screen with a flat background. The cursor seems to move as if is leaving a tail, because errors in the image data for the cursor moving in a flat density background appear far to the right from the cursor itself, changing the images there.
Further, in a flat density image, a carry-over due to error data added occurs periodically. Because of this, the position of a bright pixel and a dark pixel are coincident in each adjacent horizontal scanning line and also in respective frames. This results in the appearance of a vertical line on a display screen, deteriorating the display quality.
In order to solve this problem, image data for the present pixel is compared to that for the immediately preceding pixel.
If the difference is more than a predetermined value, it is judged that the edges of these images, namely, the previous image and the present image, do not have relevance with each other. Thus, error data which have been accumulated so far are all reset so that the previous image will not influence the present image as they are essentially different from each other.
In addition, in a flat density image, error data is reset for every certain number of pixels, the certain number being indicated by the number of bits of error data. In this event, the position of a pixel where error data is reset, that is, a reset timing is set different for every horizontal scanning line. With these arrangements, carry-over due to added error data occur in scattered places over the screen, which can prevent production of a specific pattern and residual influence of error data, resultantly improving display quality for a flat image.
A pseudo continuous tone process apparatus having the above function is disclosed in Japanese Patent Application No. Hei 6-310817 filed by the present applicant.
FIG. 2 is a block diagram showing the structure of the above -pseudo continuous tone process apparatus.
Latch circuit 11 sequentially receives eight bit original image data GD in synchronism with a dot clock DCLK and latches them. Receiving image data UGD from latch circuit 11, an operation circuit 12, which is an eight bit adding circuit, adds them and four bit error data ED from the error control circuit 13. The upper four bits of an eight bit image data outputted from operation circuit 12 are supplied to latch circuit 14 according to a dot clock DCLK and held therein before being outputted as image display data HD into a digital driver for four bit input of an LCD display. The lower four bits, on the other hand, are supplied to latch circuit 15 as error data EN to be added to image data for the next pixel. The error data EN held in circuit 15 is supplied to error control circuit 13. Image judgement circuit 16 compares respective image data GD sequentially supplied, to thereby detect an image edge, an image pattern, or the like. A detected result is supplied via a signal SEL to error control circuit 13.
Error control circuit 13 is responsible for the following operations; receiving error data EN from latch circuits 15 and outputting it to operation circuit 12 so that the operation circuit 12 carries out general error diffusion processing; resetting error data EN at a different pixel position for every horizontal scanning line; and preparing error data to be added using the error data of the lower four bits of image data GD, based on the assumption that the image data GD are maintained as the image data before an image boundary and outputting the error data prepared to the operation circuit 12.
FIG. 3 is a block diagram showing the structure of an error control circuit 13. Horizontal counter 27, a four bit counter reset by a vertical synchronous signal VSYNC, is used for detecting the present horizontal scanning line position so as to change a reset pixel position for every horizontal scanning line. To detect the present horizontal scanning line position, the counter 27 counts horizontal synchronous signals HSYNC. According to the counter value of horizontal counter 27, decoder 28 outputs data of a predetermined value. That is, it outputs data of sixteen different values for changing a reset pixel position depending on the position of a horizontal scanning line in question. The dot counter 29 is preset to a valve output from decoder 28 using horizontal synchronous signal HSYNC. Dot counter 29 is a four bit counter for incrementing a preset value according to a clock signal CLK which is synchronous to image data GD. This dot counter 29 issues a reset signal RES when all the bits of its output become "1," that is, the counter value becomes "15." Upon issuance of a reset signal RES, reset circuit 20 cuts off the error data EN of the immediately preceding pixel and instead outputs data "0" to the selection circuit 21. With data "0" supplied as errors data EN, diffusion of error data which have been accumulated thus far is reset.
Error generation circuit 22 prepares error data ED to be added to the present image data GD, based on the counter value of dot counter 29 and error data GDE of the present image data GD to be processed. To be specific, it multiplies the dot counter 29 value plus one by the error data GDE. Thus, the obtained error data ED is the one which has been computed based on the assumption that the present image data GD was continuous to the previous image data, even if in actual fact it was not. The error data ED prepared is supplied to selection circuit 21. Selection circuit 21, switched under control of a signal SEL from image judgement circuit 16, generally selects error data EN which has passed through latch circuit 15 and reset circuit 20, and outputs it to the operation circuit 12. However, if an image boundary is detected and a signal SEL is accordingly outputted, selection circuit 21 instead outputs error data ED which was prepared by error generation circuit 22 to the operation circuit 12.
In the following, resetting of error data EN and error generation in FIG. 3 will be described with reference to FIGS. 4A and 4B. FIG. 4A shows a reset pattern, in which the horizontal numbers are the numbers of pixel positions, and the vertical numbers are line numbers and preset data values. Error data EN are reset at pixels with * in this diagram. Obviously, repetition patterns are formed over a 16.times.16 pixel area as horizontal counter 26 and dot counter 29 are both of four bits. Error resetting is held for every sixteen pixels such that reset positions are displaced by three pixels between adjacent horizontal scanning lines. FIG. 4B shows by # positions where carry-over occurs (i.e., operation circuit 12 gives a carry-over to the upper four bits;) with error data EN "8" when the reset pattern shown in FIG. 4A is applied.
For instance, when horizontal counter 27 shows a counter value "1" according to a horizontal synchronous signal HSYNC, decoder 28 outputs data "14," which is then preset into dot counter 29. If one clock signal CLK is applied in the above condition, dot counter 29 turns its counter value into "15", issuing a reset signal RES. In short, error data is reset at a pixel position "1." Thereafter, dot counter 29 increments its counter value for every input of a clock signal CLK as "0, 1, 2 . . . ". In other words, the dot counter 29 value shows a distance expressed in pixels from a reset position to the present pixel. For example, if the dot counter 29 value is "5", for the pixel "7", it is assumed that the image data GD for the pixel "7" is maintained as that of the previous pixel before the image boundary, error data to be added to this image data GD becomes a six-fold value of the error data GDE of this image data GD. Therefore, error generation circuit 22 calculates error data ED to be added by multiplying a dot counter 29 value plus one by error data GDE. In cases where there is an image boundary between pixel positions "6" and "7", the image data GD for the pixel "7" is added to error data ED which was computed based on the assumption that the image data GD was maintained as that of the previous pixel. As a result, the carry-over pattern shown in the pixel "7" column in FIG. 4B is obtained, improving the display quality of an image near the boundary.
Although a single reset pattern is used in the above, a plurality of reset patterns according to error data GDE of image data GD may be prepared in actual fact. In such cases, the same number of decoders 28 and dot counters 29 as the number of reset patterns are provided so that an output of an appropriate dot counter 29 is selected depending on the value of error data DGE. For the details, refer to Japanese Patent Application No. Hei 6-310817.
When a conventional pseudo continuous tone process apparatus having the structures shown in FIGS. 1 and 2 is applied to a general VGA (Video Graphics Array) liquid crystal display having 640.times.480 pixels, the frequency of a dot clock DCLK which is synchronous to image data GD is set at about 25 MHz. By the way, as the result of recent developments in liquid crystal displays, a high precision liquid crystal display having 1024.times.768 pixels, called XGA (extended graphics array), or even 1280.times.1024 pixels has come to be in use. If the above pseudo continuous tone process apparatus is employed for such a high precision liquid crystal display, a dot clock has to have such a high frequency as 70-90 MHz, and the structures shown in FIGS. 1 and 2 may have a risk of becoming inoperative as an integrated circuit.
Next described is another conventional method for increasing the number of continuous tones displayable in a pseudo manner. In this method, an undisplayable component with one pixel is diffused into the identical pixel in the next frame (inter-frame error diffusion). To be specific, the lower bit(s) of image data in one frame which were not displayed in that frame are held as error data in a frame memory and added to the image data for the identical pixel in the next frame. Error data is thus diffused into other frames, so that pseudo continuous tones are obtained.
In this method, the image data for identical pixels in respective frames are the same in cases of a still image display. In cases of a moving image display as well, they are almost the same between adjacent frames since moving images between adjacent frames can be considered as still images. This fact is utilized in this method. That is, when the above inter-frame error diffusion process is carried out with one bit error data, a carry-over occurs for every other frame in cases of error data "1". Assuming a case where four bit image data is transformed into three bit display data, the transformation is made as follows
TABLE 1 ______________________________________ added result image inter-frame display data error data data processing ______________________________________ frame 1 0101 0101 010 non-adding frame 2 0101 0110 011 adding frame 3 0101 0101 010 non-adding frame 4 0101 0110 011 adding frame 5 0101 0101 010 non-adding . . . . . . . . . . . . ______________________________________
In this case, the lowest bit of image data keeps being added to its immediately upper bit, without holding error data, during an entire period corresponding to one frame for every other frame. With this arrangement, a frame memory is omissible.
FIG. 5 is a block diagram showing an image information process apparatus for transforming seven bit image data SD into six bit display data DG and outputting the latter. The upper six bits SD1-6 of the seven bits constituting image data are supplied to adding circuit 31 via one of the adding inputs thereof, and the lowest bit SD0 is inputted to AND gate 32 via one of the inputs thereof. AND gate 32 also receives a timing control signal ST via the other input, and supplies an output to adding circuit 31 via the other adding input. Adding circuit 31 outputs display data DG0-5 in-to a display.
The lowest bit SD0 is not added when a timing signal ST has a value "0," and it is added to its immediately upper bit when a timing signal ST has value "1." If adding is performed with respect to all the pixels in one frame for every other frame, alternation of bright and dark frames will be caused, resulting in flickering. In order to solve this problem and achieve consistent image display, adding is performed for every other pixel in the horizontal direction as well as for every other line in one frame. Further, this alternate pattern of adding and non-adding is reversed for every frame. A timing signal ST is generated by a timing signal generation circuit 33 based on the signals which the circuit 33 receives, namely, a vertical synchronous signal VSYNC, a horizontal synchronous signal HSYNC, and a dot clock DCLK synchronous to image data SD.
In the example shown in FIG. 5, image data SD is of seven bits and display data is of six bits. However, there may be liquid crystal displays which incorporate digital drivers of 3, 4, 5 or 6 bits, etc. In order to be applied to any of these displays, an image information process apparatus must include a plurality of circuits capable of handling the respective cases.
In FIG. 6, there are shown an adding circuit 34 for converting four bit image data into three bit display data, an adding circuit 35 for converting five bit image data into four bit display data, an adding circuit 36 for converting six bit image data into five bit display data, and an adding circuit 37 for converting seven bit image data into six bit display data. Outputs of these adding circuits 34, 35, 36, and 37 are selected by a selection circuit and outputted.
In operation, adding circuit 34 receives image data SD4-6 via a first group of adding inputs, namely adding inputs A0-2 and an output of AND gate 39 via one of the adding inputs constituting a second group, namely adding input BO. AND gate 39 receives image data SD3. Adding circuit 34 also receives data "0" via (the rest of the second group, namely adding inputs B1-2. Adding circuit 35 receives image data SD3-6 via a first group of adding inputs, namely adding inputs A0-3 and an output of AND gate 40 via one of the adding inputs constituting a second group, namely adding input B0. AND gate 40 receives image data SD2. Adding circuit 35 also receives data "0" via the rest of the second group, namely adding inputs B1-3. Adding circuit 36 receives image data SD2-6 via a first group of adding inputs, namely adding inputs A0-4 and an output of AND gate 41 via one of the adding inputs constituting a second group, namely adding input BO. AND gate 41 receives image data SD1. Adding circuit 36 also receives data "0" via the rest of the second group, namely via adding inputs B1-4. Adding circuit 37 receives image data SD1-6 via a first group of adding inputs, namely adding inputs A0-5 and an output of AND gate 42 via one of the adding inputs constituting a second group, namely adding input B0. AND gate 42 receives image data SD0. Adding circuit 37 also receives data "0" via the rest of the second group, namely adding inputs B1-5. AND gates 39, 40, 41, and 42 also receive a timing control signal ST via other inputs.
As described above, a plurality of adding circuits are provided so as to cope with a liquid crystal display of a different number of input bits. Those adding circuits supply their outputs to switch circuit 38, which in turn selects one of the supplied outputs according to a selection signal SEL0 or SEL1.
In the image information process apparatus shown in FIG. 6, however, even when the apparatus is working to convert seven bit image input into six bit display data, for instance, adding circuits which are not relevant to this conversion, namely adding circuits 4, 5, and 6, are also kept in an operative state. This will increase power consumption. What is worse, if the above apparatus is formed into an integrated circuit, a significant number of elements are used, increasing chip areas and thus related costs.